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IEC 60749-41-2020 pdf free download

IEC 60749-41-2020 pdf free download.Semiconductor devices — Mechanical and climatic test methods — Part 41: Standard reliability testing methods of non-volatile memory devices
Dispositifs a semiconducteurs — Méthodes d’essais mécaniques et climatiques — Partie 41: Méthodes d’essai normalisées pour Ia fiabilité des dispositifs a memoire non volatile. Data patterns during cycling
The data pattern used for endurance cycling shall be agreed upon between supplier and user, and the rationale documented. It is important to cycle enough sectors of blocks during the cycling period taking into account for the target application models. See Note 1 to Entry 3.4 for a discussion of the trade-offs involved in the selection of data pattern for cycling.
The purpose of many qualifications is to test the device for the broadest possible range of failure mechanisms. The broadest possible range of failure mechanisms can be detected when the data pattern includes the full range of logic levels and adjacency conditions that would occur in actual use. For example, this full range can be achieved if the following three conditions are met. First, the data in the memory cells is cycled between all available logic states in equal measure. For example, in an SBC memory half the cells would be programmed and half left erased in any one cycle, whereas in a 4-level cell memory one-quarter of the cells would be written to each of the four available levels in any given cycle. Second, the positions of is and Os are non-uniform, ideally quasi-random, so that all possible adjacency configurations are represented. For example, a data pattern consisting of a mix of bytes with data patterns OOH (zero zero hexadecimal), 55H, AAH, 33H, CCH, and FFH would create a wide range of adjacency patterns. Third, the data pattern in successive cycles is not the same, but rather follows a sequence. Best practice is to ensure, in this sequence, that some cells are written to all avai’able logic states while other cells are re-written to the same logic state in every cycle. For example, in an SBC memory, a byte that was cycled to AAH in even- numbered cycles and 5AH in odd-numbered cycles would have four cells that would be written to Os and is in alternating cycles, two cells that are re-written to 0 in every cycle, and two cells that are re-written to 1 in every cycle.
In some knowledge-based qualifications, endurance tests can be defined for specific failure mechanisms. Such tests can use different data patterns from that described above, optimized to increase the sensitivity to the targeted mechanisms. Examples of acceptable data patterns for such purposes include a solid programmed pattern, checkerboard/inverse-checkerboard sequence, and checkerboard with subsequent filling-in of the pattern.IEC 60749-41-2020 pdf free download.

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